Multistage amplifier

ABSTRACT

A first transistor has a first terminal and a second terminal. A second transistor has a third terminal, a fourth terminal and a fifth terminal electrically connected to the second terminal of the first transistor during amplification performed by the first transistor. A first bias circuit is electrically connected to the first terminal of the first transistor and supplies a first bias to the first terminal so that a magnitude of the first bias is increased with a rise in circuit temperature. A second bias circuit is electrically connected to the third terminal of the second transistor and supplies a second bias to the third terminal so that the magnitude of the second bias is constantly maintained with respect to changes in the circuit temperature.

BACKGROUND OF THE INVENTION Field of the Invention

The present invention relates to a multistage amplifier.

Background Art

A technique called current reuse, i.e., a technique of verticallystacking a plurality of circuits so that a current flowing in anupper-stage circuit is reused in a lower-stage circuit, is being put topractical use. Typically, with the reduction in power supply voltages toCMOS circuits, a related technique has been provided in which ahigh-withstand-voltage power supply voltage is used by verticallystacking a plurality of CMOS circuits. Typical examples of circuitsvertically stacked for current reuse in the related art are memorydevices, digital (logic) circuits and RF circuits (e.g., LNA+Buffer orVCO+MIX). A consumption current can be reduced by performing currentreuse.

A technique of performing current reuse in a multistage amplifier, forexample, as disclosed in Japanese Patent Laid-Open No. 2003-332864 isknown. In this multistage amplifier, a drain of an initial stageamplifier (initial stage amplifying transistor) and a gate of a finalstage amplifier (final stage amplifying transistor) are connected toeach other to perform multistage amplification of an input signal.Further, from the viewpoint of current reuse, a source of the finalstage amplifying transistor and the drain of initial stage amplifyingtransistor are connected to each other.

A bias circuit is connected to each of a plurality of circuitsvertically stacked for current reuse. In many cases, if a circuit whichreceives a bias has a temperature characteristic, a bias circuit adjuststhe magnitude of the bias in order to avoid degradation of the circuitcharacteristic with changes in temperature. In a case where a pluralityof circuits vertically stacked respectively have temperaturecharacteristics, bias circuits adjust the magnitudes of current biasesto the circuits in upper and lower stages so that the circuitcharacteristics do not degrade with changes in temperature. In a memorydevice or the like, circuits in an upper stage and circuits in a lowerstage in circuits vertically stacked are operated with temperaturecharacteristics equal to each other. Accordingly, in a memory device orthe like, a plurality of bias circuits change biases to circuit in anupper stage and circuit in a lower stage with the same tendency withrespect to the change of temperature.

On the other hand, in a multistage amplifier, biases may be supplied ina way different from that described above. In a multistage amplifier, asignal amplified by an initial stage amplifier is input to an amplifierin a subsequent stage. Therefore, the magnitude of the input signal ischanged between the initial stage amplifier and the subsequent stageamplifier. Due to this difference, different performance capabilitiesare required of the initial stage amplifier and the subsequent stageamplifier. In order to meet different performance requirements, it isdesirable to give certain temperature characteristic to one particularperformance capability that the initial stage amplifier has and to givea different temperature characteristic to another particular performancecapability that the subsequent stage amplifier has. This is a specificcondition irrelevant to the above-described memory device or the like.The above-described related technique lacks consideration of thisdifference, and there are still improvement points for multistageamplifiers using current reuse.

SUMMARY OF THE INVENTION

In view of the above-described problem, an object of the presentinvention is to provide a multistage amplifier having a reduced powerconsumption and good characteristics.

According to the present invention, a multistage amplifier includes: afirst transistor having a first terminal to which an input signal isinput and a second terminal from which a signal obtained by amplifyingthe input signal is output; a second transistor having a third terminalto which the signal amplified by the first transistor is input, a fourthterminal from which a signal obtained by amplifying the signal receivedby the third terminal is output and a fifth terminal electricallyconnected to the second terminal of the first transistor duringamplification performed by the first transistor; a first bias circuitelectrically connected to the first terminal of the first transistor andsupplying a first bias to the first terminal so that a magnitude of thefirst bias is increased with a rise in circuit temperature; and a secondbias circuit electrically connected to the third terminal of the secondtransistor and supplying a second bias to the third terminal so that themagnitude of the second bias is constantly maintained with respect tochanges in the circuit temperature.

According to the present invention, a multistage amplifier having areduced power consumption and good characteristics can be obtained bymaking a combination of current reuse techniques for multistageamplifiers and by adjusting biases so as to compensate for a reductionin gain due to a rise in temperature.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing a communication system including amultistage amplifier according to a first embodiment of the presentinvention.

FIG. 2 is a block diagram showing the converter including the multistageamplifier.

FIG. 3 is a circuit diagram of the multistage amplifier according to thefirst embodiment of the present invention.

FIG. 4 is a circuit diagram of the initial stage amplifier that themultistage amplifier according to the first embodiment of the presentinvention has.

FIG. 5 is a circuit diagram of the final stage amplifier that themultistage amplifier according to the first embodiment of the presentinvention has.

FIG. 6 is a circuit diagram of the second stage amplifier that themultistage amplifier according to the first embodiment of the presentinvention has.

FIG. 7 is a circuit diagram of a bias circuit used for the initial stageamplifier according to the first embodiment of the present invention.

FIG. 8 is a circuit diagram of a bias circuit used for the final stageamplifier according to the first embodiment of the present invention.

FIG. 9 is a diagram for explaining an intermediate node potential of themultistage amplifier according to the embodiment of the presentinvention.

FIGS. 10 and 11 are diagrams showing temperature characteristics of thebiases used in the multistage amplifier according to the firstembodiment of the present invention.

FIGS. 12 to 14 are diagrams showing other examples of the temperaturecharacteristics of the biases used in the multistage amplifier accordingto the first embodiment of the present invention.

FIGS. 15 and 16 are diagrams for explaining the operation of thevertically stacked multistage amplifier shown in FIG. 9.

FIGS. 17 and 18 are diagrams for explaining the effect of the multistageamplifier 10 according to the first embodiment of the present invention.

FIG. 19 is a circuit diagram of a multistage amplifier according to asecond embodiment of the present invention.

FIG. 20 is a diagram for explaining the operation of the multistageamplifier according to the second embodiment of the present invention.

FIGS. 21 and 22 are diagrams showing modified examples of the multistageamplifier according to the second embodiment of the present invention.

FIG. 23 is a circuit diagram of a multistage amplifier according to athird embodiment of the present invention.

FIGS. 24 and 25 are diagrams showing modified examples of the multistageamplifier according to the third embodiment of the present invention.

FIG. 26 is a circuit diagram of a multistage amplifier according to afourth embodiment of the present invention.

FIGS. 27 and 28 are diagrams showing output-temperature characteristicsof the first and second current sources that the multistage amplifieraccording to the fourth embodiment of the present invention has.

FIG. 29 is a diagram for explaining the operation of the multistageamplifier according to the fourth embodiment of the present invention.

FIGS. 30 to 32 are diagrams showing modified examples of the multistageamplifier according to the fourth embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment

[Configuration of Apparatus According to a First Embodiment]

FIG. 1 is a diagram showing a communication system including amultistage amplifier 10 according to a first embodiment of the presentinvention. The communication system shown in FIG. 1 has a receiver 3, atuner 106 which receives a signal from the receiver 3, and a televisionset 107 which produces, from a video signal and an audio signal from thetuner 106, a display on a screen and an output through a speaker. Thereceiver 3 has a BS antenna 4 and a converter 5 attached to the BSantenna 4. A signal from a broadcasting satellite 1 is received with theBS antenna 4 installed outdoors and displayed on the television set 107via the converter 5 and the tuner 106. The multistage amplifier 10 isincorporated in the converter 5. The converter 5 installed outdoors canbe easily influenced by atmospheric temperature and the BS antenna 4 maybe placed in a severe high-temperature or low-temperature environment.FIG. 2 is a block diagram showing the converter 5 including themultistage amplifier 10. The converter 5 includes a power amplifier 8,an oscillator 7, a mixer 6 and the multistage amplifier 10. The mixer 6outputs to the multistage amplifier 10 a signal formed by mixing anoutput signal from the power amplifier 8 and a signal from theoscillator 7. While an example of application of the multistageamplifier 10 to the BS receiving system is described in the descriptionof the first embodiment, the multistage amplifier 10 may also be appliedto a CS receiving system. Needless to say, a transmitting system canalso be constructed by incorporating the multistage amplifier 10 in atransmitter.

FIG. 3 is a circuit diagram of the multistage amplifier 10 according tothe first embodiment of the present invention. The multistage amplifier10 has an initial stage amplifier 11, a second stage amplifier 12, afinal stage amplifier 13, a bias circuit 31 for supplying a current biasto the initial stage amplifier 11 and a bias circuit 32 for supplying acurrent bias to the final stage amplifier 13 and is capable ofperforming three-stage amplification. The initial stage and second stageamplifiers 11 and 12 and the final stage amplifier 13 are verticallystacked in two stages to perform current reuse. The initial stageamplifier 11 and the second stage amplifier 12 are connected to a GNDnode and to an intermediate node 150, while the final stage amplifier 13is connected to the intermediate node 150 and to a power supply nodeVdd. In the vertical stack relationship, the initial stage amplifier 11and the second stage amplifier 12 are positioned in the “lower stage”and the final stage amplifier 13 is positioned in the “upper stage”.

In a preferred mode of the first embodiment, an “adjustment circuit” foradjusting the magnitude of a current flowing through the intermediatenode 150 so that variation in potential on the intermediate node 150 islimited is provided. In the first embodiment, the second stage amplifier12 plays a role as this adjustment circuit.

FIG. 4 is a circuit diagram of the initial stage amplifier 11 that themultistage amplifier 10 according to the first embodiment of the presentinvention has. FIG. 4 also shows the bias circuit 31 for supplying abias to the initial stage amplifier 11 as well as the initial stageamplifier 11. Any of various well-known differential amplifier circuitsmay preferably be used as initial stage amplifier 11. The differentialamplifier circuit shown in FIG. 4 by way of example has initial stageamplifying transistors Tr1 and Tr2 having their sources connected toeach other and having input signals IN+ and IN− input to their gates, aninitial stage amplifying transistor Tr3 provided between a sourceconnection point of the initial stage amplifying transistors Tr1 and Tr2and a GND node, and transistors Tr4 and Tr5 provided between drains ofthe initial stage amplifying transistors Tr1 and Tr2 and theintermediate node 150.

In this embodiment, the initial stage amplifying transistor Tr2corresponds to the “first transistor” in the present invention and has agate through which it receives input signal IN+ and a drain throughwhich it outputs an amplified signal OUT' obtained by amplifyingdifferential input signals is output. The initial stage amplifyingtransistor Tr1 has a gate through which it receives input signal IN−.The source connection point between the initial stage amplifyingtransistors Tr1 and Tr2 is connected to a drain of the initial stageamplifying transistor Tr3. A source of the initial stage amplifyingtransistor Tr3 is electrically connected to the GND node. The sourceconnection point between the initial stage amplifying transistors Tr1and Tr2 is electrically connected to the GND node through the initialstage amplifying transistor Tr3 in the on state when the initial stageamplifier 11 operates to perform amplification of an input signal.“Amplification” referred to here may be power amplification or voltageamplification.

The bias circuit 31 supplies current biases to the gates of the initialstage amplifying transistors Tr1, Tr2, and Tr3 such that the magnitudesof the biases increase with a rise in circuit temperature. Morespecifically, the bias circuit 31 includes a bias circuit 31 a and abias circuit 31 b. The transistors are different objects to which biasesare to be supplied from the bias circuit 31 a and the bias circuit 31 b,and the values of the bias voltages supplied to the transistors aredifferent from each other. The bias circuit 31 a and the bias circuit 31b, however, have the same tendency (i.e., the same temperature-outputcharacteristic) in changing the magnitudes of the biases with a changein circuit temperature and each have, for example, a characteristic Bdescribed below with reference to FIG. 11. In the descriptions of firstto fourth embodiments, therefore, a common temperature characteristic ofthe bias circuits 31 a and 31 b is described as a “temperaturecharacteristic of the bias circuit 31” for ease of description.

As shown in FIG. 4, the gates of the initial stage amplifyingtransistors Tr1 and Tr2 are connected to the bias circuit 31 a throughresistors R1 and R2, respectively. More specifically, one ends of theresistors R1 and R2 are connected to the gates of the initial stageamplifying transistors Tr1 and Tr2; the other ends of the resistors R1and R2 are connected to each other; and the point of this connection isconnected to the bias circuit 31 a. The bias circuit 31 a applies a biasvoltage Vg12 to each of the resistors R1 and R2. On the other hand, thegate of the initial stage amplifying transistor Tr3 is connected to thebias circuit 31 b through a resistor R3. Therefore, the bias circuit 31b applies a bias voltage Vg1 to the resistor R3. The values of the biasvoltages Vg1 and Vg12 are designed so that the current equal to thetotal of the currents flowing through the initial stage amplifyingtransistors Tr1 and Tr2 flows through the initial stage amplifyingtransistor Tr3. The circuit configuration and operation of thedifferential amplifier are well known and the values of the biases to beprovided for the transistors may be set on the basis of a well-knowntechnique. Therefore, no further description will be made of them.

FIG. 5 is a circuit diagram of the final stage amplifier 13 that themultistage amplifier 10 according to the first embodiment of the presentinvention has. The final stage amplifier 13 has an inductor L7, acapacitor C7, a resistor R7 and a final stage amplifying transistor Tr7.In this embodiment, the final stage amplifying transistor Tr7corresponds to the “second transistor” in the present invention. Asignal OUT″ amplified by the initial stage amplifier 11 (initial stageamplifying transistors Tr1 and Tr2) and further amplified by the secondstage amplifier 12 is input to a gate of the final stage amplifyingtransistor Tr7. From a drain of the final stage amplifying transistorTr7, a signal OUT obtained by amplifying the signal OUT″ input to thegate is output. A source of the final stage amplifying transistor Tr7 isconnected to the intermediate node 150. The source of the final stageamplifying transistor Tr7 is electrically connected to the drains of theinitial stage amplifying transistors Tr1 and Tr2 through the transistorsTr4 and Tr5 in the on state when the initial stage amplifier 11 operatesto perform signal amplification. A bias voltage Vg2 from the biascircuit 32 described below is applied to a point of connection betweenthe gate of the final stage amplifying transistor Tr7 and the capacitorC7.

FIG. 6 is a circuit diagram of the second stage amplifier 12 that themultistage amplifier 10 according to the first embodiment of the presentinvention has. A self-biased CMOS inverter shown in FIG. 6 is applied tothe second stage amplifier 12. The self-biased CMOS inverter shown inFIG. 6 has an N-type MOSFET Q1 and a P-type MOSFET Q2 complimentarilyconnected to each other, a resistor R12 and a capacitor C12. Theamplified signal OUT′ output from the initial stage amplifier 11 isinput to a point of connection between gates of the P-type MOSFET Q2 andthe N-type MOSFET Q1 through the capacitor C12. The resistor R12connects the gate connection point and a drain connection point betweenthe P-type MOSFET Q2 and the N-type MOSFET Q1 to each other. The drainconnection point between the P-type MOSFET Q2 and the N-type MOSFET Q1is an output terminal through which the amplified signal OUT″ is output.This output terminal is electrically connected to the gate of the finalstage amplifying transistor Tr7. The second stage amplifier 12 furtheramplifies the first stage amplified signal OUT′ input through the inputterminal and outputs the second stage amplified signal OUT″ to theoutput terminal.

The second stage amplifier 12 described above performs a preferablecircuit operation to adjust the amount of current flowing through theintermediate node 150 so that variation in potential on the intermediatenode 150 is limited. More specifically, the above-described second stageamplifier 12 changes the current caused to flow therethrough, on thebasis of the potential on the connection point at which the intermediatenode 150 and the second stage amplifier 12 are electrically connected toeach other. A larger current can be drawn off from the intermediate node150 through the second stage amplifier 12 by increasing the currentcaused to flow through the second stage amplifier 12. Conversely, byreducing the current caused to flow through the second stage amplifier12, the drawn current from the intermediate node 150 can be reduced toadd a current flowing from the intermediate node 150 into the initialstage amplifier 11. The second stage amplifier 12 thus performs apreferable circuit operation to add or drawn off a current at theintermediate node 150 on the basis of the potential on the connectionpoint at which the intermediate node 150 and the second stage amplifier12 are electrically connected to each other.

FIG. 7 is a circuit diagram of a bias circuit (more specifically, thebias circuit 31 b) used for the initial stage amplifier 11 according tothe first embodiment of the present invention. The bias circuit 31 b iselectrically connected to the gate of the initial stage amplifyingtransistor Tr3 through the resistor R3 to variably supply the biasvoltage Vg1. The bias circuit 31 b supplies a current bias to the gateof the initial stage amplifying transistor Tr3 so that the magnitude ofthe bias increases with a rise in circuit temperature. FIG. 7 disclosesan example of a circuit capable of supplying such a current bias. Thebias circuit 31 b has a current source I1, a transistor Tr6 having anoutput current input to its drain from the current source I1 and havingits source electrically connected to a GND node, a resistor R6 havingits one end connected to a gate of the transistor Tr6, and a capacitorC6 connected between the other end of the resistor R6 and the source ofthe transistor Tr6. The gate and drain of the transistor Tr6 areelectrically short-circuited. As current source I1, aproportional-to-absolute-temperature (PTAT) circuit having a positivetemperature coefficient is used. Various circuit configurations for PTATcircuits are known and, therefore, will not be described in thisspecification.

As described above, the bias circuit 31 in the first embodiment includesthe bias circuit 31 a and the bias circuit 31 b for adjusting themagnitudes of biases with the same temperature characteristic(characteristic B in the first embodiment, described below withreference to FIG. 11). While FIG. 7 shows an example of a circuitconfiguration for the bias circuit 31 b, a temperature-outputcharacteristic of the bias circuit 31 a having the same tendency as thebias circuit 31 b may also be realized by including in the bias circuit31 a the circuit configuration shown in FIG. 7 same as the bias circuit31 b. In any case, the same temperature-output characteristic as that ofthe bias circuit 31 b can be set for the bias circuit 31 a by using acircuit configuration such as a PTAT circuit. This makes it possible tochange the magnitudes of the biases supplied to the gates of the initialstage amplifying transistors Tr1 to Tr3 with the same tendency accordingto the circuit temperature.

FIG. 8 is a circuit diagram of a bias circuit (bias circuit 32) used forthe final stage amplifier according to the first embodiment of thepresent invention. The bias circuit 32 is electrically connected to thegate of the final stage amplifying transistor Tr7 to variably supply thebias voltage Vg2. The bias circuit 32 supplies a current bias to thegate of the final stage amplifying transistor Tr7 so that the magnitudeof the bias is constantly maintained with respect to change in circuittemperature. FIG. 8 shows an example of a circuit capable of supplyingsuch a current bias. The circuit shown in FIG. 8 is the same as the biascircuit 31 b shown in FIG. 7 except that the current source I1 isreplaced with a current source I2. The current source I2 outputs acurrent of a constant magnitude regardless of temperature. Inconstructing the bias circuit 32, any of various well-known referencevoltage circuits can be used and its circuit configuration is notrestrictively specified; a bandgap reference circuit may be used.

In the embodiment, “circuit temperature” means the internal circuittemperature in the multistage amplifier 10. For example, if there is atemperature distribution in the multistage amplifier 10, the “circuittemperature” is a typical temperature such as average temperature.Strictly speaking, each of the temperatures of the initial stageamplifying transistors Tr1, Tr2, and Tr3 of the initial stage amplifier11 and the temperature of the final stage amplifying transistor Tr7 ofthe final stage amplifier 13 is important, and the temperatures of thetransistors are not precisely equal to each other. In some cases, thereare small differences between the temperatures. In the embodiment, thetemperatures are assumed to be substantially equal to each other and aretreated collectively as “circuit temperature”. The circuit temperaturehas a positive correlation with the temperature of the multistageamplifier 10. As a package structure for the multistage amplifier 10,any of various well-known package structures can be adopted in packagingusing, for example, but not limited to, resin encapsulation or ametallic case. In any case, if the circuit temperature rises, thetemperatures of the circuit elements constituting the initial stageamplifier 11 and the final stage amplifier 13 rise and the outputcharacteristics of the initial stage amplifier 11 and the final stageamplifier 13 therefore change. For example, if the converter 5 isinstalled in various areas such as a cold climate area, a warm climatearea and a torrid area, the average and the upper and lower limit valuesof the circuit temperature in the multistage amplifier 10 vary. Even inone area, the circuit temperature varies, for example, with change inatmospheric temperature.

[Operation of the Device According to the First Embodiment]

FIG. 9 is a diagram for explaining an intermediate node potential Vmidof the multistage amplifier 10 according to the embodiment of thepresent invention. FIGS. 10 and 11 are diagrams showing temperaturecharacteristics of the biases used in the multistage amplifier 10according to the first embodiment of the present invention. Theoperation of the multistage amplifier 10 will be described by usingthese diagrams.

The temperature characteristics of the biases will first be described.For discrimination in the description, for convenience sake, thetemperature characteristic shown in FIG. 10 is also referred to as“characteristic A” and the temperature characteristic shown in FIG. 11is also referred to as “characteristic B”. A reference temperature Trefin the diagrams is a temperature used as a reference in determination ofthe temperature characteristic. The reference temperature Tref can beset to an arbitrary value in designing the amplifier. For example, roomtemperature such as an absolute temperature 300K can be used asreference temperature Tref. For convenience sake, a high temperatureregion of temperatures equal to or higher than the reference temperatureTref is also referred to as “first temperature region Thigh” and a lowtemperature region below the reference temperature Tref is also referredto as “second temperature region Tlow”.

With the characteristic A shown in FIG. 10, the magnitude of the bias isconstantly maintained with respect to change in circuit temperature. Itis preferable that the bias circuit 32 supplies the bias to the gate ofthe final stage amplifying transistor Tr7 in accordance with thecharacteristic A, because the linearity, which is one of characteristicsof the final stage amplifier 13, is well maintained thereby.

The characteristic B shown in FIG. 11 is such that the magnitude of thebias increases proportionally with a constant gradient with a rise incircuit temperature. It is preferable that the bias circuit 31 a and thebias circuit 31 b supply the bias Vg12 to the gate of the initial stagemultiplying transistor Tr1, the bias Vg12 to the gate of the initialstage multiplying transistor Tr2, and the bias Vg1 to the gate of theinitial stage multiplying transistor Tr3 in accordance with thecharacteristic B, because the gain, which is one of characteristics ofthe initial stage amplifier 11, is well maintained thereby. In general,if the bias is constant, the gain of the amplifier lowers with a rise intemperature. In biasing with the characteristic B, therefore, the biasis increased with a rise in temperature to compensate for the loweringof the gain.

With the embodiment described above, it has been demonstrated that themultistage amplifier 10 having a reduced power consumption and goodcharacteristics can be obtained by combining a current reuse techniquewith a multistage amplifier and by adjusting the biases so as tocompensate for a reduction in gain due to a rise in temperature. Even ifthe converter 5 is installed under any of various temperature conditions(e.g., in a high-temperature or low-temperature environment in which theatmospheric temperature changes largely), the multistage amplifier 10can make the most of its amplification performance.

In a case where vertically stacked circuits are arranged in aconventional memory device, a digital (logic) circuit or an RF circuit(LNA+Buffer or VCO+MIX) from the viewpoint of current reuse, currentbiases for an upper stage and a lower stage in the vertical stack areordinarily supplied with the same temperature characteristic. Amultistage amplifier, however, differs in this respect and it ispreferable to make different the temperature characteristics of currentbiases in order to satisfy characteristics respectively required of theinitial and subsequent amplifiers.

Making different the temperature characteristics of current biases fordifferent stages, however, entails a problem described below. For easeof the following description, the drain-source current of the initialstage amplifying transistor Tr3 of the initial stage amplifier 11 isassumed to be I11; the drain-source current of the MOSFETs constitutingthe second stage amplifier 12, I12; the drain-source current of thefinal stage amplifying transistor Tr7, I13.

If, as shown in FIG. 9, the second stage amplifier 12 is not provided,the operation is as described below. Since the initial stage amplifier11 and the final stage amplifier 13 are a vertically stacked currentreuse circuit, the current I11 flowing through one of them and thecurrent I13 flowing through the other influence each other.

The operation in the first temperature region Thigh above the referencetemperature Tref in the circuit shown in FIG. 9 will be considered. Thecurrent I13 is constant because the bias circuit 32 supplies the biaswith the characteristic A. However, the bias given to the initial stageamplifying transistor Tr3 of the initial stage amplifier 11 is increasedin the first temperature region Thigh above the reference temperatureTref because the bias circuit 31 (bias circuit 31 b) supplies the biaswith the characteristic B. In this case, the current I11 should beincreased. In this case, a phenomenon occurs in which the current I11transiently becomes larger than the current I13 and the intermediatenode potential Vmid lowers. Such lowering of the potential is notpreferable since the potential on the intermediate node 150 correspondsto the reference potential for the final stage amplifying transistorTr7. Otherwise the final stage amplifier 13 as the upper stage in thevertically stacked circuit limits the current I11 and there is apossibility of the initial stage amplifier 11 as the lower stage in thevertically stacked circuit failing to function normally.

The operation in the second temperature region Tlow below the referencetemperature Tref in the circuit shown in FIG. 9 will be considered. Thebias circuit 31 makes the current bias smaller than when the circuittemperature is equal to the reference temperature Tref. As a result, thecurrent I11 is reduced while the current I13 is constant; a phenomenonreverse to that described above occurs.

The inventor of the present invention conceived a technical idea ofproviding some current adjustment function to absorb the differencebetween currents I11 and I13 flowing in stages in a vertically stackedcircuit such as shown in FIG. 9. More specifically, in the firstembodiment, the second stage amplifier 12 having a circuit operation foradjusting the current flowing through the intermediate node 150 isprovided. In the embodiment, a design is made such that I13=I11+I12 atthe reference temperature Tref set to a certain temperature such as roomtemperature.

A case where the circuit temperature rises and the intermediate nodepotential Vmid lowers will first be described. The second stageamplifier 12 is a self-biased CMOS inverter. When the intermediate nodepotential Vmid lowers, the drain-source current I12 through the MOSFETsQ1 and Q2 constituting the second stage amplifier 12 is reduced. Also,in the case of biasing with the bias characteristic B shown in FIG. 11,the current I11 of the initial stage amplifier 11 should be increasedsince the circuit temperature increases. The amount of current havingfailed to flow through the second stage amplifier 12 due to the loweringof the intermediate node potential Vmid is thereby caused to flowthrough the initial stage amplifier 11. The relationship: I13=I11+I12can therefore be maintained even when the circuit temperature isincreased, thus constantly maintaining the intermediate node potentialVmid.

A case where the circuit temperature lowers and the intermediate nodepotential Vmid rises will subsequently be described. When theintermediate node potential Vmid rises, the drain-source current I12through the MOSFETs is increased in the relationship reverse to thatdescribed above. Also, in the case of biasing with the biascharacteristic B shown in FIG. 11, the current I11 of the initial stageamplifier 11 should be reduced since the circuit temperature lowers.When the intermediate node potential Vmid rises, the second stageamplifier 12 deprives the initial stage amplifier 11 of a current. Therelationship: I13=I11+I12 can thereby be maintained, thus constantlymaintaining the intermediate node potential Vmid.

FIGS. 15 and 16 are diagrams for explaining the operation of thevertically stacked multistage amplifier 10 shown in FIG. 9. In FIG. 15,the operating point at the reference temperature Tref is indicated by asolid round mark. When the circuit temperature rises, the bias circuit31 increases the bias, so that the operating point is shifted to anupper left point as indicated by an upward arrow and a leftward arrow inFIG. 15. Conversely, when the circuit temperature lowers, the biascircuit 31 reduces the bias, so that the operating point is shifted to alower right point in FIG. 15. The following description is made withreference to FIG. 16 by considering the difference between the currentsI11 and I13. The ordinate of FIG. 16 represents the difference betweenthe current through the initial stage amplifier 11 in the lower stage(i.e., current I11) and the current through the final stage amplifier 13in the upper stage (i.e., current I13) in the vertically stacked circuitshown in FIG. 9. In FIG. 16, the value on the ordinate (the value ofI11-I13) intersects the abscissa at the reference temperature Tref. Thedifference between the I11 and I13 at the reference temperature Tref isreferred to as reference value I0 for convenience sake.

In the first temperature region Thigh above the reference temperatureTref, the bias circuit 31 increases the bias. Therefore the current I11required for the initial stage amplifier 11 is higher in this regionthan at the reference value I0. On the other hand, the current flowingthrough the final stage amplifier 13 is constant since the bias from thebias circuit 32 is constant independently of the temperature. In thefirst temperature region Thigh, therefore, the value on the ordinate(i.e., the value obtained by subtracting the current I13 from thecurrent I11) becomes larger on the positive side when the temperature isincreased as shown in FIG. 16. In this situation, if the current I12through the second stage amplifier 12 is constant, the intermediate nodepotential Vmid is lowered and the intermediate node 150 is maintained atthe lowered potential. In the first embodiment, however, the current I12is reduced according to the degree of lowering of the intermediate nodepotential Vmid when the intermediate node potential Vmid lowers, sincethe second stage amplifier 12 is a self-biased CMOS inverter. Thelowering of the intermediate node potential Vmid can thus be limited.

Conversely, in the second temperature region Tlow below the referencetemperature Tref, the bias circuit 31 makes the bias lower than at thetemperature Tref. Therefore the current I11 required for the initialstage amplifier 11 is lower in this region than at the reference valueI0. On the other hand, the current I13 flowing through the final stageamplifier 13 is constant since the bias from the bias circuit 32 isconstant independently of the temperature. In the second temperatureregion Tlow, therefore, the value on the ordinate (i.e., the valueobtained by subtracting the current I13 from the current I11) becomeslarger on the negative side when the temperature is reduced as shown inFIG. 16. In this situation, if the current I12 through the second stageamplifier 12 is constant, the intermediate node potential Vmid rises andthe intermediate node 150 is maintained at the potential after the rise.In the first embodiment, however, the current I12 is increased accordingto the degree of rise in the intermediate node potential Vmid when theintermediate node potential Vmid rises, since the second stage amplifier12 is a self-biased CMOS inverter. The rise in the intermediate nodepotential Vmid can thus be limited.

In the first embodiment, as described above, an increase or reduction inthe current I12 flowing through the second stage amplifier 12 when thecurrent bias for the initial stage amplifier 11 is increased or reducedcan be added or subtracted in relation to the initial stage amplifier11. As a result, the intermediate node potential Vmid can be maintainedat the constant potential. That is, in the first embodiment, the secondstage amplifier 12 can stabilize the intermediate node potential Vmid byadjusting the current flowing through the intermediate node 150.Consequently, the multistage amplifier having a reduced powerconsumption and good characteristics can be operated with stability.

Since the adjustment is performed on the basis of the intermediate nodepotential Vmid, the intermediate node potential Vmid can be adjustedeven when variation in intermediate node potential Vmid is caused due tomanufacturing variation. It is thus possible to make use of theadvantage of the function of adjusting the intermediate node potentialVmid in such a case as well as in the case where the current bias ischanged with temperature.

When the bias circuit 31 increases the bias with a rise in temperature,the multistage amplifier 10 operates, for example, as described below.First, it is assumed that, in an initial state, the current I11 flowingthrough the initial stage amplifier 11 is 10 mA, the current I12 flowingthrough the second stage amplifier 12 is 20 mA and the current I13flowing through the final stage amplifier 13 is 30 mA. Next, it isassumed that the bias circuit 31 increases the bias with a rise intemperature so that the current flowing through the initial stageamplifier 11 is 12 mA. A change of the current I12 flowing through thesecond stage amplifier 12 to a minus 2 mA from the initial state, i.e.,a change of the current I12 flowing through the second stage amplifier12 to 18 mA, suffices for supply of the current of a plus 2 mA to theinitial stage amplifier 11. Simultaneously with this rise intemperature, the current as seen in the initial stage amplifier 11 is20% increased and the current as seen in the second stage amplifier 12is 10% reduced. The change in current in the second stage amplifier 12is gentler than the change in current in the initial stage amplifier 11.That is, when a change in temperature occurs, the rate of change inoutput current (10%) in the second stage amplifier 12 with a change inthe bias from the bias circuit 31 is lower than the rate of change inoutput current (20%) in the initial stage amplifier 11. Also, while theinitial stage amplifier 11 is a differential amplifier, the second stageamplifier 12 is a CMOS inverter. There is a difference in gaincharacteristic therebetween due to the difference between the circuitconfigurations. The balance between the currents respectively flowingthrough the initial stage amplifier 11 and the second stage amplifier 12may be adjusted by considering these points while satisfying performancerequirements with respect to the entire multistage amplifier 10. Thenumeric values shown above are only a concrete example, to which thepresent invention is not limited.

Comparison with the circuit configuration disclosed in Japanese PatentLaid-Open No. 2003-332864 will be made for description of the advantageof use of the self-biased CMOS inverter in the first embodiment. Acurrent Is0 is drawn off through a resistor Rs0 from a connection pointcorresponding to the intermediate node in Japanese Patent Laid-Open No.2003-332864. The amount of current drawn off through the resistor Rs0changes linearly with respect to a change in potential (ΔV) (that is,I=ΔV/R). On the other hand, the self-biased CMOS inverter operates inaccordance with the current square law on the basis of thecurrent-voltage characteristic of the MOSFETs. That is, the self-biasedCMOS inverter can change the amount of drawn-off current as the secondpower of a change in potential (i.e., I∞ΔV^2). In the first embodiment,the second stage amplifier 12, i.e., the self-biased CMOS inverter,functions to adjust the current flowing through the intermediate node150. Advantageously, therefore, the effect of maintaining theintermediate node potential Vmid is high.

FIGS. 17 and 18 are diagrams for explaining the effect of the multistageamplifier 10 according to the first embodiment of the present invention.FIG. 17 is a graph when the current changing linearly with respect to achange in potential (ΔV) was drawn off by connecting a resistor to theintermediate node 150 as in the case of the technique according toJapanese Patent Laid-Open No. 2003-332864. FIG. 18 shows the results ofadjustment of the current through the intermediate node 150 performed byusing the self-biased CMOS inverter, which corresponds to the operationof the multistage amplifier 10 according to the first embodiment. Asdescribed above, the self-biased CMOS inverter can change the current asthe second power of a change in potential (i.e., I∞ΔV^2). The resultingcharacteristics shown in FIG. 18 are better than those shown in FIG. 17.More specifically, the initial stage amplifier 11 has a positivetemperature characteristic as its current characteristic 101. The actualcurrent characteristic 100 of the final stage amplifier 13 has a smallgradient in comparison with the flat ideal current characteristic 103 ofthe final stage amplifier 13. Referring to FIG. 17, the intermediatenode potential changes by 0.5 V in a temperature region from minus 50°C. to plus 100° C. Referring to FIG. 18, the change in intermediate nodepotential Vmid in the same temperature region is limited to 0.22 V.

FIGS. 12 to 14 are diagrams showing other examples of the temperaturecharacteristics of the biases used in the multistage amplifier 10according to the first embodiment of the present invention. Fordiscrimination in the description, for convenience sake, the temperaturecharacteristic shown in FIG. 12 is also referred to as “characteristicC”, the temperature characteristic shown in FIG. 13 as “characteristicD”, and the temperature characteristic shown in FIG. 14 as“characteristic E”.

(Characteristic C)

With characteristic C shown in FIG. 12, the magnitude of the bias isconstantly maintained with respect to the circuit temperature in thefirst temperature region Thigh of temperatures equal to or higher thanthe predetermined reference temperature Tref. In the second temperatureregion Tlow below the reference temperature Tref, the bias is increasedwith reduction in the circuit temperature. The circuit configuration ofthe bias circuit 32 may be designed to have this characteristic C. Morespecifically, a temperature characteristic of the current source I2 maybe designed. An effect of improving the linearity of the amplifier canbe obtained by increasing the bias with reduction in circuit temperaturein the second temperature region Tlow on the lower temperature side.

(Characteristic D)

With characteristic D shown in FIG. 13, the bias is increased with arise in circuit temperature in the first temperature region Thigh oftemperatures equal to or higher than the predetermined referencetemperature Tref. In the second temperature region Tlow below thereference temperature Tref, the bias is constantly maintained withrespect to the circuit temperature. The circuit configuration of thebias circuit 31 may be designed to have this characteristic D. Morespecifically, a temperature characteristic of the current source I1 maybe designed.

(Characteristic E)

With characteristic E shown in FIG. 14, the bias circuit 31 increasesthe bias with a rise in circuit temperature in the first temperatureregion Thigh of temperatures equal to or higher than the predeterminedreference temperature Tref. With characteristic E, in the secondtemperature region Tlow, the bias is increased with reduction in circuittemperature. That is, a temperature characteristic is exhibited in“V-shaped” form on the current-temperature characteristic graph with alower limit peak value at the reference temperature Tref. The circuitconfiguration of the bias circuit 31 may be designed to have thischaracteristic E. More specifically, a temperature characteristic of thecurrent source I1 may be designed.

The bias circuit 32 may change the magnitude of the current bias withcharacteristic A (FIG. 10) or characteristic C (FIG. 12). The biascircuit 31 may change the magnitude of the current bias with one ofcharacteristics B to D (FIG. 11, FIG. 13, FIG. 14). Thus, a combinationof “characteristic A” and “one of characteristics B, D, and E” or acombination of “characteristic C” and “one of characteristics B, D, andE” is possible.

In the first embodiment, the second stage amplifier 12 can adjust thecurrent on the basis of the intermediate node potential Vmid. With anyselection from the above-described characteristics A to E as thecharacteristics of the bias circuit 31 and the bias circuit 32,therefore, variation in intermediate node potential Vmid can be limited.

In designing the bias circuits having certain ones of thecharacteristics C to E, suitable ones of various well-known techniquesincluding, for example, the above-mentioned PTAT and bandgap referencemay be used. Therefore, concrete circuit configurations, designparameters of circuit elements, etc., will not be described.

Second Embodiment

FIG. 19 is a circuit diagram of a multistage amplifier 110 according toa second embodiment of the present invention. The multistage amplifier110 according to the second embodiment is formed by adding an adjustmentcircuit 130 while removing the second stage amplifier 12. That is, atwo-stage amplifier is formed in the second embodiment. In otherrespects, the configuration of the amplifier provided in the secondembodiment is the same as that of the amplifier 10 according to thefirst embodiment described above. Various modifications described abovewith respect to the first embodiment can also be made in the same waywith respect to the second embodiment. The same modifications in thesecond embodiment will not be described. Since a configuration similarto that in the first embodiment is provided, biases are also adjustedwith the bias circuit 31 in the second embodiment so as to compensatefor a reduction in gain due to a rise in temperature. The multistageamplifier having a reduced power consumption and good characteristicscan therefore be obtained, as in the case of the first embodiment.

The adjustment circuit 130 performs a preferable circuit operation toadjust the amount of current flowing through the intermediate node 150so that variation in potential on the intermediate node 150 is limited,as does the second stage amplifier 12 in the first embodiment. Morespecifically, the adjustment circuit 130 performs a preferable circuitoperation to add or drawn off a current at the intermediate node 150 onthe basis of the potential on the connection point at which theintermediate node 150 and the adjustment circuit 130 are electricallyconnected to each other.

The adjustment circuit 130 has a current adding circuit 131 and acurrent drawing-off circuit 132. The current adding circuit 131 includesan upper stage transistor 121 (the third transistor according to thepresent invention) and an upper stage operational amplifier 133. Theupper stage transistor 121 has a drain, a gate and a source to beelectrically connected to the power supply potential. A positive inputto the upper stage operational amplifier 133 is electrically connectedto the intermediate node 150. An output from the upper stage operationalamplifier 133 is supplied to the gate of the upper stage transistor 121.

The current drawing-off circuit 132 includes a lower stage transistor122 (the fourth transistor according to the present invention) and alower stage operational amplifier 134. The lower stage transistor 122has a drain electrically connected to the drain of the upper stagetransistor 121, a source to be electrically connected to the GND node,i.e., the reference potential, and a gate. The point of connectionbetween the drain of the upper stage transistor 121 and the drain of thelow stage transistor 122 is electrically connected to the intermediatenode 150. The positive input of the lower stage operational amplifier134 is electrically connected to the intermediate node 150. Thereference voltage Vref is applied to a negative input of the lower stageoperational amplifier 134. An output from the lower stage operationalamplifier 134 is supplied to the gate of the lower stage transistor 122.

FIG. 20 is a diagram for explaining the operation of the multistageamplifier 110 according to the second embodiment of the presentinvention. The upper stage transistor 121 functions as a switch forcontrolling electrical conduction between the power supply node Vdd andthe intermediate node 150, and adjusts the amount of current added atthe intermediate node 150. The lower stage transistor 122 functions as aswitch for controlling electrical conduction between the intermediatenode 150 and the GND node, and adjusts the amount of current drawn offfrom the intermediate node 150. When the intermediate node potentialVmid deviates from the reference voltage Vref, one of the operationalamplifiers opens the switch to enable the necessary amount of current toflow until the intermediate potential (3) becomes substantially equal tothe reference voltage (4).

FIGS. 21 and 22 are diagrams showing modified examples of the multistageamplifier 110 according to the second embodiment of the presentinvention. To a multistage amplifier 111 shown in FIG. 21 and amultistage amplifier 112 shown in FIG. 22, a second stage amplifier 120and a bias circuit 33 are added, thereby enabling three-stageamplification. The second stage amplifier 120, however, is not thesecond stage amplifier 12 (self-biased CMOS inverter) according to thefirst embodiment but a combination of, for example, a circuit such asshown in FIG. 4 or 5 and a bias circuit 33 such as shown in FIG. 6. Theoutput characteristic of the bias circuit 33 is made, for example, thesame as that of the bias circuit 31.

Referring to FIG. 21, the number of stages in which components arestacked is three. The connection relationship when the components arevertically stacked and connected in three stages may be such that eachof the electrical connection between the initial stage amplifier 11 andthe second stage amplifier 120 and the electrical connection between thesecond stage amplifier 120 and the final stage amplifier 13 is the sameas the connection relationship when the initial stage amplifier 11 andthe final stage amplifier 13 are connected as shown in FIG. 19. In thiscase, two adjustment circuits each identical to the adjustment circuit130 shown in FIG. 19 are used. That is, adjustment circuits 130 a and130 b are provided. With the adjustment circuit 130 a, a potential Vmid1at a first intermediate node 151 at which the initial stage amplifier 11and the second stage amplifier 120 are connected to each other isadjusted so as to be equal to a reference voltage Vref1. With theadjustment circuit 130 b, a potential Vmid2 at a second intermediatenode 152 at which the second stage amplifier 120 and the final stageamplifier 13 are connected to each other is adjusted so as to be equalto a reference voltage Vref2.

Referring to FIG. 22, the number of stages in which components arestacked is two. This corresponds to a form having the second stageamplifier 120 in place of the second stage amplifier 12 in the firstembodiment.

Third Embodiment

FIG. 23 is a circuit diagram of a multistage amplifier 210 according toa third embodiment of the present invention. The multistage amplifier210 according to the third embodiment is formed by replacing theadjustment circuit 130 with an adjustment circuit 50 including an upperstage diode series circuit 51 and a lower stage diode series circuit 52.In other respects, the configuration of the amplifier provided in thethird embodiment is the same as that of the multistage amplifier 110according to the second embodiment described above. Variousmodifications described above with respect to the first embodiment canalso be made in the third embodiment. Also in the third embodiment,biases are adjusted with the bias circuit 31 as in the case of the firstembodiment so as to compensate for a reduction in gain due to a rise intemperature. The multistage amplifier having a reduced power consumptionand good characteristics can therefore be obtained, as in the case ofthe first embodiment.

The upper stage diode series circuit 51 and the lower stage diode seriescircuit 52 perform a preferable circuit operation to adjust the amountof current flowing through the intermediate node 150 so that variationin potential on the intermediate node 150 is limited, as does the secondstage amplifier 12 in the first embodiment or the adjustment circuit 130in the second embodiment. More specifically, the upper stage diodeseries circuit 51 and the lower stage diode series circuit 52 perform apreferable circuit operation to add or drawn off a current at theintermediate node 150 on the basis of the potential on the connectionpoint at which the intermediate node 150 and the upper stage and lowerstage diode series circuits 51 and 52 are electrically connected to eachother.

The lower stage diode series circuit 52 is formed by electricallyconnecting a plurality of diodes one to another in the forwarddirection, and corresponds to the current drawing-off circuit accordingto the third embodiment. The upper stage diode series circuit 51 isformed by electrically connecting a plurality of diodes one to anotherin the forward direction, and corresponds to the current adding circuitaccording to the third embodiment. A connection point between the anodeend of the lower stage diode series circuit 52 and the cathode end ofthe upper stage diode series circuit 51 is electrically connected to theintermediate node 150. The cathode end of the lower stage diode seriescircuit 52 is electrically connected to the sources of the initial stageamplifying transistors Tr1 and Tr2. The sources of the initial stageamplifying transistors Tr1 and Tr2 are electrically connected to thereference potential terminal while the initial stage amplifier 11 isoperating, as described above. The anode end of the upper stage diodeseries circuit 51 is electrically connected to the drain of the finalstage amplifying transistor Tr7.

When the intermediate node potential Vmid lowers, the potentialdifference between the opposite ends of the upper stage diode seriescircuit 51 becomes larger. When the potential difference between theopposite ends of the upper stage diode series circuit 51 becomes equalto or larger than the sum of the forward voltages of all the diodesconstituting the upper stage diode series circuit 51, a current flowsthrough the upper stage diode series circuit 51. The current is therebyadded at the intermediate node 150. After the current starts flowing, alarger amount of current can be added at the intermediate node 150 ifthe potential on the intermediate node 150 is lower. When theintermediate node potential Vmid rises, the potential difference betweenthe opposite ends of the lower stage diode series circuit 52 becomeslarger. When the potential difference between the opposite ends of thelower stage diode series circuit 52 becomes equal to or larger than thesum of the forward voltages of all the diodes constituting the lowerstage diode series circuit 52, a current flows through the lower stagediode series circuit 52. As a result, the current is drawn off from theintermediate node 150. After the current starts flowing, a larger amountof current can be drawn off from the intermediate node 150 if thepotential on the intermediate node 150 is higher.

By making use of this, addition or drawing-off of a current at theintermediate node 150 can be performed when the intermediate nodepotential Vmid deviates from a voltage designed in advance. Each of thevoltage when a current flows through the lower stage diode seriescircuit 52 and the voltage when a current flows through the upper stagediode series circuit 51 can be adjusted to the desired value by means ofthe forward voltage of the diodes and the number of diodes in the seriesconnection. However, the adjustable voltage is limited to an integermultiple of the forward voltage.

FIGS. 24 and 25 are diagrams showing modified examples (multistageamplifiers 211 and 212) of the multistage amplifier 210 according to thethird embodiment of the present invention. In each modified example, thesecond stage amplifier 120 and the bias circuit 33 are added andthree-stage amplification is performed. Referring to FIG. 24, the numberof stages in which components are stacked is three, as in the case shownin FIG. 21. Referring to FIG. 25, the number of stages in whichcomponents are stacked is two, as in the case shown in FIG. 22. Themultistage amplifier 211 in FIG. 24 has an adjustment circuit 53 havingdiode series circuits 54, 55, and 56 stacked in three stages.

Fourth Embodiment

FIG. 26 is a circuit diagram of a multistage amplifier 310 according toa fourth embodiment of the present invention. The multistage amplifier310 according to the fourth embodiment is formed by replacing theadjustment circuit 130 with an adjustment circuit 420. In otherrespects, the configuration of the amplifier provided in the fourthembodiment is the same as that of the multistage amplifier 110 accordingto the second embodiment described above. Various modificationsdescribed above with respect to the first embodiment can also be made inthe fourth embodiment. Also in the fourth embodiment, biases areadjusted with the bias circuit 31 so as to compensate for a reduction ingain due to a rise in temperature. The multistage amplifier having areduced power consumption and good characteristics can therefore beobtained, as in the case of the first embodiment.

The adjustment circuit 420 performs a preferable circuit operation toadjust the amount of current flowing through the intermediate node 150so that variation in potential on the intermediate node 150 is limited,as do the second stage amplifier 12 in the first embodiment, theadjustment circuit 130 in the second embodiment, and the adjustmentcircuit 50 in the third embodiment. The fourth embodiment, however,differs from the first to third embodiments in the following respect. Inthe first to third embodiments, addition and drawing-off of a current atthe intermediate node 150 are performed in a feedback manner on thebasis of the potential on the point of connection to the intermediatenode 150. In the fourth embodiment, the adjustment circuit 420 is addedwhich performs a current addition/current drawing-off operation reverseto the operation of the bias circuit 31 in opposition to the biascircuit 31 changing the bias with reference to the circuit temperature.

As shown in FIG. 26, the adjustment circuit 420 includes a verticallystacked circuit having a first current source 421 provided in an upperstage and a second current source 422 provided in a lower stage. Aconnection point between the first current source 421 and the secondcurrent source 422 is electrically connected to the intermediate node150.

FIGS. 27 and 28 are diagrams showing output-temperature characteristicsof the first and second current sources 421 and 422 that the multistageamplifier 310 according to the fourth embodiment of the presentinvention has. The first current source 421 outputs a current to theintermediate node 150. As shown in FIG. 27, the first current source 421increases the current flowing into the intermediate node 150 if thecircuit temperature is increased when the circuit temperature is equalto or higher than the predetermined reference temperature Tref. Thefirst current source 421 thereby adds the current at the intermediatenode 150.

On the other hand, the second current source 422 is electricallyconnected to the intermediate node 150 and draws off a current from theintermediate node 150. As shown in FIG. 28, the second current source422 increases the output current value if the circuit temperature lowerswhen the circuit temperature is lower than the reference temperatureTref. The second current source 422 thereby draws off the current fromthe intermediate node 150 while increasing the current if the circuittemperature lowers.

FIG. 29 is a diagram for explaining the operation of the multistageamplifier 310 according to the fourth embodiment of the presentinvention. In the case where the operation of the first current source421 and the operation of the second current source 422 are combined, thefirst current source 421 adds a larger current on the higher temperatureside of the reference temperature Tref, so that a deficiency of currentin the initial stage amplifier 11 can be limited. Also, the secondcurrent source 422 draws off a larger current on the lower temperatureside of the reference temperature Tref, so that a surplus current isenabled to escape to the GND node. As a result, the magnitude of thecurrent flowing through the intermediate node 150 can tend to increasemonotonously with increase in temperature through both the firsttemperature region Thigh and the second temperature region Tlow, asshown in the graph of FIG. 29.

The provision of the two current sources having differentcharacteristics on the high temperature side and the low temperatureside for the adjustment circuit 420 also ensures the followingadvantage. In the high temperature region as defined about the referencetemperature Tref indicated in FIG. 29, a current is produced from thepower supply node Vdd and supplied to the intermediate node 150. In thisregion, therefore, the entire consumption current is increased. On theother hand, in the low temperature region, the second current source 422only causes a surplus current to flow to the GND node, with the firstcurrent source 421 not operated. Since the first current source 421 isnot operated, the consumption current as a whole is constant. Asdescribed above, the current flowing through the intermediate node 150is increased only in the high temperature region side relative to thereference temperature Tref when the potential on the intermediate node150 is adjusted, thus enabling current saving in the low temperatureregion side.

FIGS. 30 and 31 are diagrams showing modified examples of the multistageamplifier 310 according to the fourth embodiment of the presentinvention. Each of a multistage amplifier 311 shown in FIG. 30 and amultistage amplifier 312 shown in FIG. 31 has the second stage amplifier120 and the bias circuit 33 added thereto and performs three-stageamplification. Referring to FIG. 30, the number of stages in whichcomponents are stacked is two, as in the case shown in FIG. 22.Referring to FIG. 31, the number of stages in which components arestacked is three, as in the case shown in FIG. 21. An adjustment circuit450 provided in the arrangement shown in FIG. 31 has current sources 451and 452 vertically stacked in two stages. The current source 451 mayhave the same temperature characteristic as that of the current source421 described above with reference to FIG. 26, and the current resource452 may have the same temperature characteristic as that of the currentsource 422 described with reference to FIG. 26. The characteristics maybe determined so that the amounts of current added and the amounts ofcurrent drawn off at the intermediate nodes 151 and 152 are changed insuch directions as to limit variations in intermediate node potentialsVmid1 and Vmid2.

As described above with respect to the first embodiment, the biascircuit 32 may have characteristic A (FIG. 10) or characteristic C (FIG.12) as its output characteristic, and the bias circuit 31 may have oneof characteristics B to D (FIG. 11, FIG. 13, FIG. 14) as its outputcharacteristic. A combination of “characteristic A” and “one ofcharacteristics B, D, and E” or a combination of “characteristic C” and“one of characteristics B, D, and E” is possible. Modifications of theadjustment circuit 420 accompanying modifications of the bias circuit 31and the bias circuit 32 will be described below.

In a case where a combination of characteristic A and characteristic Dis provided, the operation on the higher temperature side of thereference temperature Tref is the same as that in the fourth embodimentdescribed above. In the operation on the lower temperature side of thereference temperature Tref, current drawing-off accompanying a change intemperature is unnecessary because each of the biases from the biascircuits 31 and 32 is constant. Accordingly, current addition with thecurrent source 421 may be performed only in the first temperature regionThigh on the higher temperature side of the reference temperature Tref,and the current source 422 may be removed from the adjustment circuit420.

In a case where a combination of characteristic A and characteristic Eis provided, the operation in the first temperature region Thigh on thehigher temperature side of the reference temperature Tref is the same asthat in the fourth embodiment described above. On the other hand, theoperation in the second temperature region Tlow on the lower temperatureside of the reference temperature Tref differs from that in the fourthembodiment. That is, the bias circuit 31 operates with characteristic Eand should therefore cause a larger current to flow from theintermediate node 150 into the initial stage amplifier 11 when thetemperature lowers, while the bias circuit 32 constantly maintains thebias. In the case where the combination of characteristic A andcharacteristic E is provided, therefore, a current which becomes moreinsufficient with reduction in temperature relative to the referencetemperature Tref is increased in the second temperature region Tlow. Forexample, the current source 422 may have a characteristic shown in FIG.32 instead of the characteristic shown in FIG. 28. If the current source422 has such a characteristic, it limits drawing-off of a current whenthe temperature lowers in the second temperature region Tlow, therebyenabling providing a current in surplus at the intermediate node 150 andsupplying the surplus current to the initial stage amplifier 11.

In a case where a combination of characteristic C and characteristic Bis provided, the operation in the higher temperature side of thereference temperature Tref is the same as that in the fourth embodimentdescribed above. On the other hand, the operation in the lowertemperature side of the reference temperature Tref is such that when thetemperature lowers, the bias circuit 32 increases the bias and the biascircuit 31 reduces the bias with reduction in temperature. Due to this,a surplus current at the intermediate node 150 is increased incomparison with the fourth embodiment. It is preferable to use thecurrent source 422 with a higher set current change rate (steepergradient) in comparison with the characteristic shown in FIG. 28 inorder to cause such a surplus current to flow to the GND node.

In a case where a combination of characteristic C and characteristic Dis provided, the circuit shown in FIG. 26 can be used. In the case wherea combination of characteristic C and characteristic D is provided, theoperation in the higher temperature side of the reference temperatureTref is the same as that in the fourth embodiment described above. Theoperation in the lower temperature side of the reference temperatureTref is such that when the circuit temperature lowers, the bias to thefinal stage amplifier 13 is increased and the amount of current to becaused to flow into the intermediate node 150 is increased. On the otherhand, the current to be supplied from the intermediate node 150 to theinitial stage amplifier 11 (more specifically, the drain-source currentof the initial stage amplifying transistors Tr1 and Tr2) is constantsince the bias to the initial stage amplifier 11 is constant on thelower temperature side of the reference temperature Tref. Therefore, theamount of surplus current at the intermediate node 150 is increased whenthe temperature is reduced. This surplus current may be caused to flowto the GND node through the current source 422. This operation is thesame as the operation of the circuit shown in FIG. 26.

In a case where a combination of characteristic C and characteristic Eis provided, the operation in the higher temperature side of thereference temperature Tref is the same as that in the fourth embodimentdescribed above. The operation in the lower temperature side of thereference temperature Tref is such that both the biases to the initialstage amplifier 11 and to the final stage amplifier 13 are increasedsimilarly to each other when the circuit temperature lowers. As aresult, both the current to be caused to flow into the intermediate node150 and the current to be drawn off from the intermediate node 150 areincreased and the intermediate node 150 becomes stable. Therefore, theoperation of the adjustment circuit 420 is not required on the lowertemperature side; the current source 422 may be removed from theadjustment circuit 420.

Obviously many modifications and variations of the present invention arepossible in the light of the above teachings. It is therefore to beunderstood that within the scope of the appended claims the inventionmay be practiced otherwise than as specifically described.

The entire disclosure of Japanese Patent Application No. 2015-109040,filed on May 28, 2015 including specification, claims, drawings andsummary, on which the Convention priority of the present application isbased, is incorporated herein by reference in its entirety.

What is claimed is:
 1. A multistage amplifier comprising: a firsttransistor having a first terminal to which an input signal is input anda second terminal from which a signal obtained by amplifying the inputsignal is output; a second transistor having a third terminal to whichthe signal amplified by the first transistor is input, a fourth terminalfrom which a signal obtained by amplifying the signal received by thethird terminal is output and a fifth terminal electrically connected tothe second terminal of the first transistor during amplificationperformed by the first transistor; a first bias circuit electricallyconnected to the first terminal of the first transistor and supplying afirst bias to the first terminal so that a magnitude of the first biasis increased with a rise in circuit temperature; and a second biascircuit electrically connected to the third terminal of the secondtransistor and supplying a second bias to the third terminal so that themagnitude of the second bias is constantly maintained with respect tochanges in the circuit temperature, wherein the second terminal and thefifth terminal are electrically connected to an intermediate node, andthe multistage amplifier further comprises an adjustment circuit tochange an amount of a current flowing through the intermediate node sothat a current flowing in the second terminal of the first transistordiffers from a current flowing through the fourth terminal and the fifthterminal of the second transistor.
 2. The multistage amplifier accordingto claim 1, wherein a variation in potential on the intermediate node islimited.
 3. The multistage amplifier according to claim 2, wherein theadjustment circuit performs addition or drawing-off of a current at theintermediate node on the basis of a potential on a connection point atwhich the intermediate node and the adjustment circuit are electricallyconnected to each other.
 4. The multistage amplifier according to claim3, wherein the adjustment circuit includes a self-biased CMOS inverterhaving an input terminal electrically connected to the second terminalof the first transistor and an output terminal electrically connected tothe third terminal of the second transistor, the self-biased CMOSinverter amplifying a signal input to the input terminal and outputtingthe amplified signal through the output terminal.
 5. The multistageamplifier according to claim 2, wherein the adjustment circuit includes:a current adding circuit which, when the potential on the intermediatenode is equal to or lower than a predetermined value, increases acurrent added at the intermediate node if the potential on theintermediate node is reduced; and a current drawing-off circuit which,when the potential on the intermediate node exceeds the predeterminedvalue, increases a current drawn off from the intermediate node if thepotential on the intermediate node is increased.
 6. The multistageamplifier according to claim 5, wherein the current adding circuitincludes: a third transistor having a first drain, a first gate and afirst source to be electrically connected to a power supply potential;and a first operational amplifier having a positive input electricallyconnected to the intermediate node and a negative input to which apredetermined reference voltage is applied, the first operationalamplifier applying an output to the first gate, wherein the currentdrawing-off circuit includes: a fourth transistor having a second drainelectrically connected to the first drain, a second source to beelectrically connected to a reference potential, a second gate, and aconnection point between the first drain and the second drain beingelectrically connected to the intermediate node; and a secondoperational amplifier having a positive input electrically connected tothe intermediate node and a negative input to which the referencevoltage is applied, the second operational amplifier applying an outputto the second gate.
 7. The multistage amplifier according to claim 5,wherein the first transistor has another terminal electrically connectedto a reference potential terminal; the current drawing-off circuitincludes a lower stage diode series circuit formed by electricallyconnecting a plurality of diodes one to another in a forward direction;the current adding circuit includes an upper stage diode series circuitformed by electrically connecting a plurality of diodes one to anotherin a forward direction; a connection point between an anode end of thelower stage diode series circuit and a cathode end of the upper stagediode series circuit is electrically connected to the intermediate node;a cathode end of the lower stage diode series circuit is electricallyconnected to the another terminal of the first transistor; and an anodeend of the upper stage diode series circuit is electrically connected tothe fourth terminal of the second transistor.
 8. The multistageamplifier according to claim 1, wherein the first bias circuit increasesthe first bias if the circuit temperature rises in a first temperatureregion of temperature equal to or higher than a predetermined referencetemperature, and constantly maintains the magnitude of the first biaswith respect to the circuit temperature in a second temperature regionof temperature below the reference temperature or increases the firstbias if the circuit temperature lowers in the second temperature region,and the second bias circuit constantly maintains the magnitude of thesecond bias through the first temperature region and the secondtemperature region.
 9. The multistage amplifier according to claim 1,wherein the second bias circuit constantly maintains the magnitude ofthe second bias with respect to the circuit temperature in a firsttemperature region of temperature equal to or higher than apredetermined reference temperature, and increases the second bias ifthe circuit temperature lowers in a second temperature region oftemperature below the reference temperature, and the first bias circuitincreases the magnitude of the first bias if the circuit temperaturebecomes higher in the first temperature region, and changes the firstbias in the second temperature region with one of a first tendency toreduce the magnitude of the first bias if the circuit temperaturebecomes lower, a second tendency to constantly maintain the magnitude ofthe first bias with respect to the circuit temperature, and a thirdtendency to increase the magnitude of the first bias if the circuittemperature becomes lower.
 10. The multistage amplifier according toclaim 2, wherein the adjustment circuit includes a current sourceelectrically connected to the intermediate node, and the current sourcechanges an output current so that the current flowing into theintermediate node is increased if the circuit temperature rises.
 11. Themultistage amplifier according to claim 10, wherein the current sourceincludes: a first current source which outputs a current to theintermediate node and increases the current flowing into theintermediate node if the circuit temperature becomes higher when thecircuit temperature is equal to or higher than a predetermined referencetemperature; and a second current source which is electrically connectedto the intermediate node, and which draws off a current from theintermediate node by increasing an output current value if the circuittemperature becomes higher when the circuit temperature is lower thanthe reference temperature.